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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity nor_gate is
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                 generic ( width : positive;
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                           Tpd01, Tpd10 : delay_length );
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                 port ( input : in std_logic_vector(0 to width - 1);
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                        output : out std_logic );
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               end entity nor_gate;
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               architecture primitive of nor_gate is
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                 function max ( a, b : delay_length ) return delay_length is
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                 begin
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                   if a > b then
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                     return a;
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                   else
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                     return b;
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                   end if;
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                 end function max;
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               begin
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                 reducer : process (input) is
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                                             variable result : std_logic;
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                 begin
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                   result := '0';
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                   for index in input'range loop
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                     result := result or input(index);
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                   end loop;
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                   if not result = '1' then
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                     output <= not result after Tpd01;
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                   elsif not result = '0' then
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                     output <= not result after Tpd10;
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                   else
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                     output <= not result after max(Tpd01, Tpd10);
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                   end if;
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                 end process reducer;
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               end architecture primitive;
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               library ieee;  use ieee.std_logic_1164.all;
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               library cell_lib;
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               entity interlock_control is
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               end entity interlock_control;
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-- code from book
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               architecture detailed_timing of interlock_control is
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                 component nor_gate is
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                                      generic ( input_width : positive );
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                                    port ( input : in std_logic_vector(0 to input_width - 1);
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                                           output : out std_logic );
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                 end component nor_gate;
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                 for ex_interlock_gate : nor_gate
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                   use entity cell_lib.nor_gate(primitive)
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                   generic map ( width => input_width,
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                                 Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
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                 -- . . .
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                 -- not in book
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                 signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
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                 -- end not in book
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               begin
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                 ex_interlock_gate : component nor_gate
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                   generic map ( input_width => 2 )
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                   port map ( input(0) => reg_access_hazard,
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                              input(1) => load_hazard,
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                              output => stall_ex_n);
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                 -- . . .
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                 -- not in book
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                 reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
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                 load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
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                                '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
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                                '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
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                                '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
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                 -- end not in book
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               end architecture detailed_timing;
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-- end code from book