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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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configuration computer_structure of computer_system is
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  for structure
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    for interface_decoder : decoder_2_to_4
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      use entity work.decoder_3_to_8(basic)
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        generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
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        port map ( s0 => in0, s1 => in1, s2 => '0',
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                   enable => '1',
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                   y0 => out0, y1 => out1, y2 => out2, y3 => out3,
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                   y4 => open, y5 => open, y6 => open, y7 => open );
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    end for;
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    -- . . .
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  end for;
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end configuration computer_structure;