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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_ch_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_13_01 is
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end entity ch_13_01;
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architecture test of ch_13_01 is
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  -- code from book
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  component nand3 is
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                    port ( a, b, c : in bit := '1';  y : out bit );
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  end component nand3;
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  -- end code from book
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  signal s1, s2, s3 : bit;
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begin
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  -- code from book
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  gate1 : component nand3
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    port map ( a => s1, b => s2, c => open, y => s3 );
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  -- end code from book
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end architecture test;
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-- code from book
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entity nand2 is
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  port ( a, b : in bit := '1';  y : out bit );
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end entity nand2;
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-- end code from book
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configuration ch_13_01_test of ch_13_01 is
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  for test
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    -- code from book
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    for gate1 : nand3
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      use entity work.nand2(basic);
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    end for;
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    -- end code from book
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  end for;
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end configuration ch_13_01_test;