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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_09_ch_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_09_01 is
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end entity ch_09_01;
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----------------------------------------------------------------
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architecture test of ch_09_01 is
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begin
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  process_09_1_a : process is
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                             -- code from book:
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                             type register_array is array (0 to 15) of bit_vector(31 downto 0);
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                           type register_set is record
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                                                  general_purpose_registers : register_array;
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                                                  program_counter : bit_vector(31 downto 0);
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                                                  program_status : bit_vector(31 downto 0);
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                                                end record;
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                           variable CPU_registers : register_set;
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                           -- code revised to work around MTI bugs mt015 and mt016
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                           -- alias PSW is CPU_registers.program_status;
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                           -- alias PC is CPU_registers.program_counter;
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                           -- alias GPR is CPU_registers.general_purpose_registers;
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                           alias PSW : bit_vector(31 downto 0) is CPU_registers.program_status;
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                           alias PC : bit_vector(31 downto 0) is CPU_registers.program_counter;
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                           alias GPR : register_array is CPU_registers.general_purpose_registers;
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                           -- alias SP is CPU_registers.general_purpose_registers(15);
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                           alias SP : bit_vector(31 downto 0) is CPU_registers.general_purpose_registers(15);
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                           -- alias interrupt_level is PSW(30 downto 26);
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                           alias interrupt_level : bit_vector(30 downto 26) is PSW(30 downto 26);
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                           -- end revision
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                           -- end of code from book
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                           procedure procedure_09_1_b is
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                             -- code from book:
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                             -- code revised to work around MTI bug mt016
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                             -- alias SP is GPR(15);
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                             alias SP : bit_vector(31 downto 0) is GPR(15);
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                             -- end revision
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                             alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
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                             -- end of code from book
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                           begin
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                           end procedure procedure_09_1_b;
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  begin
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    wait;
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  end process process_09_1_a;
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end architecture test;