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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_15 is
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end entity fg_07_15;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of fg_07_15 is
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  -- code from book
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  procedure generate_clock ( signal clk : out std_ulogic;
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                             constant Tperiod, Tpulse, Tphase : in time ) is
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  begin
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    wait for Tphase;
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    loop
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      clk <= '1', '0' after Tpulse;
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      wait for Tperiod;
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    end loop;
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  end procedure generate_clock;
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  -- end code from book
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  -- code from book (in text)
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  signal phi1, phi2 : std_ulogic := '0';
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  -- . . .
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  -- end code from book
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begin
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  -- code from book (in text)
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  gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
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                              Tphase => 0 ns );
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  gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
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                              Tphase => 25 ns );
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  -- end code from book
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end architecture test;