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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_14 is
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end entity fg_07_14;
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architecture test of fg_07_14 is
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  -- code from book
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  procedure check_setup ( signal data, clock : in bit;
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                          constant Tsu : in time ) is
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  begin
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    if clock'event and clock = '1' then
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      assert data'last_event >= Tsu
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        report "setup time violation" severity error;
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    end if;
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  end procedure check_setup;
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  -- end code from book
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  signal ready, phi2 : bit := '0';
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  constant Tsu_rdy_clk : delay_length := 4 ns;
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begin
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  -- code from book (in text)
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  check_ready_setup : check_setup ( data => ready, clock => phi2,
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                                    Tsu => Tsu_rdy_clk );
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  -- end code from book
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  clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
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  stimulus : ready <= '1' after 4 ns,
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                      '0' after 56 ns,
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                      '1' after 87 ns,
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                      '0' after 130 ns;
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end architecture test;