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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity flipflop is
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  generic ( Tsetup : delay_length );
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  port ( clk, d : in bit;  q : out bit );
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end entity flipflop;
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-- code from book
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architecture behavior of flipflop is
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begin
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  timing_check : process (clk) is
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  begin
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    if clk = '1' then
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      assert d'last_event >= Tsetup
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        report "set up violation detected in " & timing_check'path_name
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        severity error;
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    end if;
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  end process timing_check;
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  -- . . .    -- functionality
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end architecture behavior;
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-- end code from book
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entity fg_20_05 is
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end entity fg_20_05;
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architecture test of fg_20_05 is
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  signal clk, d, q : bit;
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begin
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  dut : entity work.flipflop(behavior)
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    generic map ( Tsetup => 3 ns )
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    port map ( clk => clk, d => d, q => q );
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  clk <= '1' after 10 ns, '0' after 20 ns;
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  d <= '1' after 8 ns;
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end architecture test;