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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_regm.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.dlx_types.all;
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entity reg_multiple_out is
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  generic ( num_outputs : positive;
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            Tpd : delay_length );
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  port ( d : in dlx_word;
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         q : out dlx_word_array(1 to num_outputs);
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         latch_en : in std_logic;
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         out_en : in std_logic_vector(1 to num_outputs) );
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end entity reg_multiple_out;