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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               package serial_interface_defs is
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                 subtype reg_address_vector is std_logic_vector(1 downto 0);
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                 constant status_reg_address : reg_address_vector := B"00";
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                 constant control_reg_address : reg_address_vector := B"01";
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                 constant rx_data_register : reg_address_vector := B"10";
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                 constant tx_data_register : reg_address_vector := B"11";
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                 subtype data_vector is std_logic_vector(7 downto 0);
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                 -- . . .    -- other useful declarations
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                 component serial_interface is
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                                              port ( clock_phi1, clock_phi2 : in std_logic;
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                                                     serial_select : in std_logic;
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                                                     reg_address : in reg_address_vector;
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                                                     data : inout data_vector;
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                                                     interrupt_request : out std_logic;
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                                                     rx_serial_data : in std_logic;
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                                                     tx_serial_data : out std_logic );
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                 end component serial_interface;
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               end package serial_interface_defs;