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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_tovec-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture behavioral of to_vector is
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begin
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  behavior : process (r) is
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                           variable temp : integer range -2**15 to 2**15 - 1;
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                         variable negative : boolean;
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                         variable result : std_ulogic_vector(vec'range);
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  begin
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    -- scale to [-2**15, +2**15) and convert to integer
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    if r * real(2**15) < real(-2**15) then
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      temp := -2**15;
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    elsif r * real(2**15) >= real(2**15 - 1) then
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      temp := 2**15 - 1;
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    else
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      temp := integer(r * real(2**15));
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    end if;
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    negative := temp < 0;
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    if negative then
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      temp := -(temp + 1);
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    end if;
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    result := (others => '0');
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    for index in result'reverse_range loop
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      result(index) := to_X01(bit'val(temp rem 2));
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      temp := temp / 2;
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      exit when temp = 0;
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    end loop;
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    if negative then
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      result := not result;
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      result(result'left) := '1';
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    end if;
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    vec <= result;
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  end process behavior;
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end architecture behavioral;