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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_05_12 is
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end entity fg_05_12;
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architecture test of fg_05_12 is
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  signal a, z : bit;
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begin
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  -- code from book
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  asym_delay : process (a) is
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                             constant Tpd_01 : time := 800 ps;
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                           constant Tpd_10 : time := 500 ps;
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  begin
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    if a = '1' then
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      z <= transport a after Tpd_01;
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    else  -- a = '0'
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      z <= transport a after Tpd_10;
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    end if;
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  end process asym_delay;
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  -- end code from book
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  stimulus : process is
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  begin
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    a <= '1' after 2000 ps,
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         '0' after 4000 ps,
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         '1' after 6000 ps,
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         '0' after 6200 ps;
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    wait;
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  end process stimulus;
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end architecture test;