Project

General

Profile

Download (2.42 KB) Statistics
| Branch: | Tag: | Revision:
1 d93979b7 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_04_ch_04_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
entity ch_04_07 is
28
29
end entity ch_04_07;
30
31
32
----------------------------------------------------------------
33
34
35
architecture test of ch_04_07 is
36
begin
37
38
39
  process_04_3_a : process is
40
41
                             -- code from book:
42
43
                             subtype pixel_row is bit_vector (0 to 15);
44
                           variable current_row, mask : pixel_row;
45
46
                           -- end of code from book
47
48
  begin
49
50
    current_row := "0000000011111111";
51
    mask := "0000111111110000";
52
53
    -- code from book:
54
55
    current_row := current_row and not mask;
56
    current_row := current_row xor X"FFFF";
57
58
    -- end of code from book
59
60
    -- code from book (conditions only):
61
62
    assert B"10001010" sll 3  =  B"01010000";
63
    assert B"10001010" sll -2  =  B"00100010";
64
65
    assert B"10010111" srl 2  = B"00100101";
66
    assert B"10010111" srl -6  =  B"11000000";
67
68
    assert B"01001011" sra 3  =  B"00001001";
69
    assert B"10010111" sra 3  =  B"11110010";
70
    assert B"00001100" sla 2  =  B"00110000";
71
    assert B"00010001" sla 2  =  B"01000111";
72
73
    assert B"00010001" sra -2  =  B"01000111";
74
    assert B"00110000" sla -2  =  B"00001100";
75
76
    assert B"10010011" rol 1  =  B"00100111";
77
    assert B"10010011" ror 1  =  B"11001001";
78
79
    assert "abc" & 'd'  =  "abcd";
80
    assert 'w' & "xyz"  =  "wxyz";
81
    assert 'a' & 'b'  =  "ab";
82
83
    -- end of code from book
84
85
    wait;
86
  end process process_04_3_a;
87
88
89
end architecture test;