Project

General

Profile

Download (2.81 KB) Statistics
| Branch: | Tag: | Revision:
1 d93979b7 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_04_ch_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
entity ch_04_06 is
28
29
end entity ch_04_06;
30
31
32
----------------------------------------------------------------
33
34
35
--library ieee;  use ieee.std_logic_1164.std_ulogic;
36
library ieee;  use ieee.std_logic_1164.all;
37
38
architecture test of ch_04_06 is
39
40
  -- code from book:
41
42
  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
43
  
44
  --
45
  
46
  subtype std_ulogic_word is std_ulogic_vector(0 to 31);
47
  
48
  --
49
  
50
  signal csr_offset : std_ulogic_vector(2 downto 1);
51
52
  -- end of code from book
53
54
begin
55
56
57
  process_04_2_b : process is
58
59
                             -- code from book:
60
61
                             type string is array (positive range <>) of character;
62
63
                           --
64
65
                           constant LCD_display_len : positive := 20;
66
                           subtype LCD_display_string is string(1 to LCD_display_len);
67
                           variable LCD_display : LCD_display_string := (others => ' ');
68
69
                           --
70
71
                           type bit_vector is array (natural range <>) of bit;
72
73
                           --
74
75
                           subtype byte is bit_vector(7 downto 0);
76
77
                           --
78
79
                           variable channel_busy_register : bit_vector(1 to 4);
80
81
                           --
82
83
                           constant ready_message  : string := "Ready     ";
84
85
                           --
86
87
                           variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
88
89
                           --
90
91
                           constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
92
93
                           -- end of code from book
94
95
  begin
96
97
    -- code from book:
98
99
    channel_busy_register := b"0000";
100
101
    -- end of code from book
102
103
    wait;
104
  end process process_04_2_b;
105
106
107
end architecture test;