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d93979b7
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Arnaud Dieumegard
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity display_manager is
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generic
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(
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---- For implementation:
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-- g_clock_cycle_per_display: natural := 125000
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---- For testing, we recommend using:
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g_clock_cycle_per_display: natural := 2
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);
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port
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(
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i_clock: in std_logic; -- System clock.
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i_reset: in std_logic; -- System reset.
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i_curr_0001_time: in natural range 0 to 9; -- Centiseconds
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i_curr_0010_time: in natural range 0 to 9; -- deciseconds
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i_curr_0100_time: in natural range 0 to 9; -- seconds
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i_curr_1000_time: in natural range 0 to 5; -- decaseconds
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o_display: out natural range 0 to 9; -- number on display
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o_an: out std_logic_vector (3 downto 0) -- selected display
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);
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end display_manager;
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architecture Behavioral of display_manager is
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-- Types --------------------------------------------------------------------
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-- Our display has four seven-segments components, each of which corresponds
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-- to one of these states.
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type t_display_index is (D0001, D0010, D0100, D1000);
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-- We have to count the number of clock cycles so we alternate between each
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-- seven-segment display neither too fast for the hardware, neither too slow
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-- for the human eye. This is the durationg for each seven-segment.
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-- Signals ------------------------------------------------------------------
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-- Which seven-segment we are currently drawing.
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signal futur_state: t_display_index;
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signal current_state: t_display_index;
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-- Timer to know when to switch to another seven-segment.
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signal display_timer: natural range 1 to g_clock_cycle_per_display;
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begin
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P_DISPLAY_MUX : process
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(
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current_state,
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i_curr_0001_time,
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i_curr_0010_time,
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i_curr_0100_time,
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i_curr_1000_time
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)
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begin
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o_an <= B"1111";
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case current_state is
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when D0001 => -- Centiseconds -----------------------------------------
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o_an(3) <= '0';
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futur_state <= D0010;
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o_display <= i_curr_0001_time;
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when D0010 => -- Deciseconds ------------------------------------------
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o_an(2) <= '0';
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futur_state <= D0100;
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o_display <= i_curr_0010_time;
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when D0100 => -- Seconds ---------------------------------------------
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o_an(1) <= '0';
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futur_state <= D1000;
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o_display <= i_curr_0100_time;
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when others => -- Decaseconds & Shenanigans ---------------------------
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o_an(0) <= '0';
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futur_state <= D0001;
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o_display <= i_curr_1000_time;
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end case;
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end process;
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P_TIME_COUNTER: process (i_clock, i_reset)
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begin
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if (i_reset = '1')
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then
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display_timer <= 1;
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else
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if (rising_edge(i_clock))
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then
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if (display_timer >= g_clock_cycle_per_display)
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then
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display_timer <= 1;
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else
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display_timer <= (display_timer + 1);
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end if;
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end if;
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end if;
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end process;
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P_FSM_STATE_SWITCH: process (i_clock, i_reset)
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begin
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if (i_reset = '1')
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then
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current_state <= D0001;
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else
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if (rising_edge(i_clock))
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then
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if (display_timer >= g_clock_cycle_per_display)
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then
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current_state <= futur_state;
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end if;
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end if;
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end if;
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end process;
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end;
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