CristalCaveGem » LustreC » Lustrec-Tests

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-- BEST CHRONOMETER EVER -------------------------------------------------------

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library IEEE;

-- Required by the use of "std_logic_vector".

use IEEE.STD_LOGIC_1164.ALL;

entity best_chronometer_ever is

   port

   (

      i_clock:       in std_logic;

      i_reset:       in std_logic;

      i_start_bp:    in std_logic;

      i_raz_bp:      in std_logic;

      o_display:     out std_logic_vector (6 downto 0);

      o_an:          out std_logic_vector (3 downto 0)

   );

end best_chronometer_ever;

architecture Behavioral of best_chronometer_ever is

   -- Signals ------------------------------------------------------------------

   signal new_centisecond: std_logic;

   signal raz:             std_logic;

   signal enable:          std_logic;

   signal limit_reached:   std_logic;

   signal synced_start_bp: std_logic;

   signal synced_raz_bp:   std_logic;

   signal numeral_display: natural range 0 to 9;

   signal curr_0001_time:  natural range 0 to 9;

   signal curr_0010_time:  natural range 0 to 9;

   signal curr_0100_time:  natural range 0 to 9;

   signal curr_1000_time:  natural range 0 to 5;

   -- Components ---------------------------------------------------------------

   component centisecond_timer is

      generic

      (

      ---- For implementation:

      --  g_clock_cycle_per_centisecond: natural := 500000

      ---- For testing, we recommend using:

          g_clock_cycle_per_centisecond: natural := 8

      );

      port

      (

         i_clock:           in std_logic; -- System clock.

         i_reset:           in std_logic; -- System reset.

         i_raz:             in std_logic; -- User triggered raz.

         i_enable:          in std_logic; -- Time is passing.

         o_new_centisecond: out std_logic -- Centisecond pulse.

      );

   end component;

   component crossdomain_sync is

      port

      (

         i_clock:    in std_logic;  -- System clock.

         i_reset:    in std_logic;  -- System reset.

         i_signal:   in std_logic;  -- Asynchronous signal.

         o_signal:   out std_logic  -- Synchronous signal.

      );

   end component;

   component display_manager is

      generic

      (

      ---- For implementation:

      --  g_clock_cycle_per_display: natural := 125000

      ---- For testing, we recommend using:

          g_clock_cycle_per_display: natural := 2

      );

      port

      (

         i_clock:          in std_logic;                       -- System clock.

         i_reset:          in std_logic;                       -- System reset.

         i_curr_0001_time: in natural range 0 to 9;            -- Centiseconds

         i_curr_0010_time: in natural range 0 to 9;            -- deciseconds

         i_curr_0100_time: in natural range 0 to 9;            -- seconds

         i_curr_1000_time: in natural range 0 to 5;            -- decaseconds

         o_display:        out natural range 0 to 9;           -- number on display

         o_an:             out std_logic_vector (3 downto 0)   -- selected display

      );

   end component;

   component numeral_to_display is

      generic

      (

      -- To be moved into a converter.

         g_display_value_0:         std_logic_vector(6 downto 0) := B"0000001";

         g_display_value_1:         std_logic_vector(6 downto 0) := B"1001111";

         g_display_value_2:         std_logic_vector(6 downto 0) := B"0010010";

         g_display_value_3:         std_logic_vector(6 downto 0) := B"0000110";

         g_display_value_4:         std_logic_vector(6 downto 0) := B"1001100";

         g_display_value_5:         std_logic_vector(6 downto 0) := B"0100100";

         g_display_value_6:         std_logic_vector(6 downto 0) := B"0100000";

         g_display_value_7:         std_logic_vector(6 downto 0) := B"0001111";

         g_display_value_8:         std_logic_vector(6 downto 0) := B"0000000";

         g_display_value_9:         std_logic_vector(6 downto 0) := B"0000100";

         g_display_value_error:     std_logic_vector(6 downto 0) := B"0110000"

      );

      port

      (

         i_numeral_time: in natural range 0 to 9;     -- numeral input

         o_display:  out std_logic_vector(6 downto 0) -- display output

      );

   end component;

   component time_wizard is

      port

      (

         i_clock:             in std_logic;

         i_reset:             in std_logic;

         i_raz:               in std_logic;

         i_new_centisecond:   in std_logic;

         o_limit_reached:     out std_logic;

         o_curr_0001_time:    out natural range 0 to 9;

         o_curr_0010_time:    out natural range 0 to 9;

         o_curr_0100_time:    out natural range 0 to 9;

         o_curr_1000_time:    out natural range 0 to 5

      );

   end component;

   component user_handler is

      port

      (

         i_clock:             in std_logic;  -- System's clock.

         i_reset:             in std_logic;  -- System reset.

         i_synced_start_btn:  in std_logic;  -- User input. Synchronized.

         i_synced_raz_btn:    in std_logic;  -- User input. Synchronized.

         i_limit_reached:     in std_logic;  -- Time Wizard has reached limit.

         o_enable:            out std_logic; -- Enable time passing.

         o_raz:               out std_logic  -- Reset system.

      );

   end component;

begin

   START_BP_SYNCHRONIZER: crossdomain_sync port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_signal => i_start_bp,

      o_signal => synced_start_bp

   );

   RAZ_BP_SYNCHRONIZER: crossdomain_sync port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_signal => i_raz_bp,

      o_signal => synced_raz_bp

   );

   CNTSCD_TM: centisecond_timer port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_raz => raz,

      i_enable => enable,

      o_new_centisecond => new_centisecond

   );

   DSPLY_MGR: display_manager port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_curr_0001_time => curr_0001_time,

      i_curr_0010_time => curr_0010_time,

      i_curr_0100_time => curr_0100_time,

      i_curr_1000_time => curr_1000_time,

      o_display => numeral_display,

      o_an => o_an

   );

   DSPLY_TRSLTR: numeral_to_display port map

   (

      i_numeral_time => numeral_display,

      o_display => o_display

   );

   TM_WZRD: time_wizard port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_raz => raz,

      i_new_centisecond => new_centisecond,

      o_limit_reached => limit_reached,

      o_curr_0001_time => curr_0001_time,

      o_curr_0010_time => curr_0010_time,

      o_curr_0100_time => curr_0100_time,

      o_curr_1000_time => curr_1000_time

   );

   USR_HNDLR: user_handler port map

   (

      i_clock => i_clock,

      i_reset => i_reset,

      i_synced_start_btn => synced_start_bp,

      i_synced_raz_btn => synced_raz_bp,

      i_limit_reached => limit_reached,

      o_enable => enable,

      o_raz => raz

   );

end;