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d93979b7
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Arnaud Dieumegard
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-- Company : CNES
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-- Author : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES.
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-- Licensing : GNU GPLv3
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-- Version : V1
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-- Version history :
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-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
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-- File name : CNE_05200_good.vhd
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-- File Creation date : 2015-04-14
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-- Project name : VHDL Handbook CNES Edition
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-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Multiplexor direct assertion based: good example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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-- demonstrating good practices in VHDL and as such, its design is minimalistic.
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-- It is provided as is, without any warranty.
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-- This example is compliant with the Handbook version 1.
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--
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-- Naming conventions:
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--CODE
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entity CNE_05200_good is
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port (
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i_A : in std_logic; -- First Mux input
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i_B : in std_logic; -- Second Mux input
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i_S : in std_logic; -- Mux select
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o_O : out std_logic -- Mux output
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);
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end CNE_05200_good;
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architecture Behavioral of CNE_05200_good is
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begin
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o_O <= i_A when (i_S='0')
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else i_B;
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end Behavioral;
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--CODE
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