CristalCaveGem » LustreC » Lustrec-Tests

library ieee;

use ieee.std_logic_1164.all;

entity ppg is

  port (

    LoadDelay : in integer;

    LoadLength : in integer;

    Data : in std_logic_vector (0 to 7);

    reset : in std_logic;

    clk : in std_logic;

    pulse : out std_logic

  );

end ppg;

architecture ppg1 of ppg is

  signal out_pulse : std_logic := '0';

  signal in_delay : integer := LoadDelay;

  signal in_length : integer := LoadLength;

begin

  p : process (reset, clk)

  begin

    if (clk'event and clk = '1') 

    then

      if (reset = '1')

      then

        out_pulse <= '0';

        in_delay <= LoadDelay;

        in_length <= LoadLength;

      else

        if (in_delay = 0)

        then

          if (in_length > 0) then

            in_length <= in_length - 1;

            out_pulse <= '1';

          else

            in_length <= LoadLength;

            in_delay <= LoadDelay;

            out_pulse <= '0';

          end if;

        else

          in_delay <= in_delay - 1;

        end if;

      end if;

    end if;

  end process p;

  pulse <= out_pulse;

end ppg1;