lustrec-tests/vhdl_json/vhdl_files/valencia/prep_latch_gen.vhd @ a0f656ac
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package typedef is |
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subtype byte is bit_vector (7 downto 0); |
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end; |
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use work.typedef; |
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entity data_path is |
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port (clk, rst, s_1: in boolean; s0, s1: in bit; d0, d1, d2, d3: in byte; |
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q: out byte); |
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end; |
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architecture behavior of data_path is |
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signal reg,shft : byte; |
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signal sel : bit_vector (1 downto 0); |
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begin
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process (clk,rst) is |
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begin
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if (rst) then |
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reg <= x"00"; |
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shft <= x"00"; |
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elsif ((clk and clk'event)) then |
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sel <= (s0 & s1); |
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case sel is |
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when b"00" => reg <= d0; |
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when b"10" => reg <= d1; |
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when b"01" => reg <= d2; |
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when b"11" => reg <= d3; |
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end case; |
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if (s_1) then |
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shft <= (shft(6 downto 0) & shft(7)); |
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end if; |
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end if; |
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end process; |
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q <= shft; |
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end; |