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------------------------------------------
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-- PREP Benchmark Circuit #1: Data Path
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--
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-- Copyright 1993, Data I/O Corporation.
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--
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-- Copyright 1993, Metamor, Inc.
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--
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package typedef is
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subtype byte is bit_vector (7 downto 0);
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end;
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use work.typedef.all;
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entity data_path is
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port (clk,rst,s_1 : in boolean;
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s0, s1 : in bit;
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d0, d1, d2, d3 : in byte;
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q : out byte);
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end data_path;
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architecture behavior of data_path is
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signal reg,shft : byte;
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signal sel: bit_vector(1 downto 0);
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begin
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process (clk,rst)
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begin
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if rst then -- async reset
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reg <= x"00";
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shft <= x"00";
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elsif clk and clk'event then -- define a clock
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sel <= s0 & s1;
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case sel is -- mux function
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when b"00" => reg <= d0;
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when b"10" => reg <= d1;
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when b"01" => reg <= d2;
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when b"11" => reg <= d3;
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end case;
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if s_1 then -- conditional shift
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shft <= shft(6 downto 0) & shft (7);
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else
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shft <= reg;
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end if;
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end if;
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end process;
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q <= shft;
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end behavior;
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