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1
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--- Adapted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15
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2
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3
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-- main entity
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4
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entity reg4 is
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5
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port (d0, d1, d2, d3, en, clk: in bit;
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6
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q0, q1, q2, q3 : out bit );
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end entity reg4;
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8
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9
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-- main archi
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10
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architecture behav of reg4 is
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11
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begin
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12
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q1 <= '1';
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13
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storage: process (d0, d1, d2, d3, en, clk) is
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14
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variable stored_d0, stored_d1, stored_d2, stored_d3: bit;
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15
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begin
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16
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if en = '1' and clk = '1' then
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17
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stored_d0 := d0;
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18
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stored_d1 := d1;
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stored_d2 := d2;
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20
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stored_d3 := d3;
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21
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end if;
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q0 <= stored_d0 after 5 ns;
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q1 <= stored_d1 after 5 ns;
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q2 <= stored_d2 after 5 ns;
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q3 <= stored_d3 after 5 ns;
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26
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end process storage;
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end architecture behav;
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28
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29
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-- D-latch
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entity d_latch is
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port (d, clk: in bit; q: out bit);
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32
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end entity d_latch;
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33
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34
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architecture basic of d_latch is
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35
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begin
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36
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latch_behavior : process (clk, d) is
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37
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begin
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38
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if clk = '1' then
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39
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q <= d after 2 ns;
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40
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end if;
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41
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end process latch_behavior;
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42
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end architecture basic;
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43
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44
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-- and-gate
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45
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entity and2 is
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46
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port (a, b: in bit; y: out bit);
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47
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end entity and2;
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48
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49
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architecture basic of and2 is
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50
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begin
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51
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-- and2_behavior: process (a) is
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52
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and2_behavior: process (a,b) is
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53
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begin
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54
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y <= a and b after 2 ns;
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55
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end process and2_behavior;
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56
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end architecture basic;
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57
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58
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-- Main archi
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59
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architecture struct of reg4 is
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60
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signal int_clk: bit;
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61
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signal mem: bit;
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62
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begin
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63
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q0 <= d0 and mem;
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64
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mem <= not d1;
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65
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q1 <= d2 and (not mem) and d3;
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66
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bit0: entity work.d_latch(basic)
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port map (d0, int_clk, q0);
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68
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bit1: entity work.d_latch(basic)
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69
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port map (q => q1, d => d1, clk => int_clk);
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70
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bit2: entity work.d_latch(basic)
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71
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port map (d2, int_clk, q2);
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72
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bit3: entity work.d_latch(basic)
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73
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port map (d3, int_clk, q3);
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74
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gate: entity work.and2(basic)
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75
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port map (en, clk, int_clk);
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76
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end architecture struct;
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