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Revision 928e4486

Added by Arnaud Dieumegard over 3 years ago

Test file update for typo

View differences:

vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd
73 73
end architecture struct;
74 74

  
75 75
-- Elaborated archi
76
-- architecture struct of ref4 is
76
-- architecture struct of reg4 is
77 77
--   signal int_clk: bit;
78 78
--   begin
79 79
--     bit0_latch_behavior : process (int_clk, d0) is

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