CristalCaveGem » LustreC » Lustrec-Tests

--- Extracted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15

-- main entity

entity reg4 is

  port (d0, d1, d2, d3, en, clk: in bit; 

        q0, q1, q2, q3 : out bit );

end entity reg4;

-- main archi

architecture behav of reg4 is

  begin

    storage: process (d0, d1, d2, d3, en, clk) is

      variable stored_d0, stored_d1, stored_d2, stored_d3: bit;

    begin

      if en = '1' and clk = '1' then

        stored_d0 := d0;

        stored_d1 := d1;

        stored_d2 := d2;

        stored_d3 := d3;

      end if;

      q0 <= stored_d0 after 5 ns;

      q1 <= stored_d1 after 5 ns;

      q2 <= stored_d2 after 5 ns;

      q3 <= stored_d3 after 5 ns;

      wait;

    end process storage;

end architecture behav;

-- D-latch

entity d_latch is

  port (d, clk: in bit; q: out bit);

end entity d_latch;

architecture basic of d_latch is

begin

  latch_behavior : process (clk, d) is

  begin

    if clk = '1' then

      q <= d after 2ns;

    end if;

    wait;

  end process latch_behavior;

end architecture basic;

-- and-gate

entity and2 is

  port (a, b: in bit; y: out bit);

end entity and2;

architecture basic of and2 is

  begin

  and2_behavior: process (a,b) is

  begin

    y <= a and b after 2ns;

    wait;

  end process and2_behavior;

gnd architecture basic;

-- Main archi

architecture struct of reg4 is

  signal int_clk: bit;

  begin

    bit0: entity work.d_latch(basic)

    port map (d0, int_clk, q0);

    bit1: entity work.d_latch(basic)

    port map (d1, int_clk, q1);

    bit2: entity work.d_latch(basic)

    port map (d2, int_clk, q2);

    bit3: entity work.d_latch(basic)

    port map (d3, int_clk, q3);

    gate: entity work.and2(basic)

    port map (en, clk, int_clk);

end architecture struct;

-- Elaborated archi

--   begin

--     bit0_latch_behavior : process (int_clk, d0) is

--     begin

--       if int_clk = '1' then

--         q0 <= d0 after 2ns;

--       end if;

--       wait;

--     end process bit0_latch_behavior;

--     bit1_latch_behavior : process (int_clk, d1) is

--     begin

--       if int_clk = '1' then

--         q1 <= d1 after 2ns;

--       end if;

--       wait;

--     end process bit1_latch_behavior;

--     bit2_latch_behavior : process (int_clk, d2) is

--     begin

--       if int_clk = '1' then

--         q2 <= d2 after 2ns;

--       end if;

--       wait;

--     end process bit2_latch_behavior;

--     bit3_latch_behavior : process (int_clk, d3) is

--     begin

--       if int_clk = '1' then

--         q3 <= d3 after 2ns;

--       end if;

--       wait;

--     end process bit3_latch_behavior;

--     gate_and2_behavior: process (en, clk) is

--     begin

--       int_clk <= en and clk after 2ns;

--       wait;

--     end process gate_and2_behavior;

-- end architecture struct;