ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/forth-cpu/uart.vhd
ERROR: Parse error at line 164 column 3:

154:     wrote_n    <= '1';
155:    elsif din_ack = '0' and wrote_c = '1' then
156:    --elsif wrote_c = '1' then
157:     -- assert din_ack = '1' on the next cycle?
158:     din_stb    <= '1';
159:     wrote_n    <= '0';
160:    end if;
161:  end process;
162: 
163:  rx_fifo: work.util.fifo
164:   generic map (
       ^
165:    data_width => 8,
166:    fifo_depth => fifo_depth)
167:   port map(
168:    clk   => clk,
169:    rst   => rst,
170:    di    => dout,
171:    we    => dout_stb,
172:    re    => rx_data_re,
173:    do    => rx_data,
174:    full  => rx_fifo_full,

WARN: Missing blame information for the following files:
WARN:   * uart.vhd
WARN: This may lead to missing/broken features in SonarQube