1
|
|
2
|
-- Copyright (C) 2001 Bill Billowitch.
|
3
|
|
4
|
-- Some of the work to develop this test suite was done with Air Force
|
5
|
-- support. The Air Force and Bill Billowitch assume no
|
6
|
-- responsibilities for this software.
|
7
|
|
8
|
-- This file is part of VESTs (Vhdl tESTs).
|
9
|
|
10
|
-- VESTs is free software; you can redistribute it and/or modify it
|
11
|
-- under the terms of the GNU General Public License as published by the
|
12
|
-- Free Software Foundation; either version 2 of the License, or (at
|
13
|
-- your option) any later version.
|
14
|
|
15
|
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
|
16
|
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
17
|
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
18
|
-- for more details.
|
19
|
|
20
|
-- You should have received a copy of the GNU General Public License
|
21
|
-- along with VESTs; if not, write to the Free Software Foundation,
|
22
|
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
23
|
|
24
|
-- ---------------------------------------------------------------------
|
25
|
--
|
26
|
-- $Id: tc1310.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
|
27
|
-- $Revision: 1.2 $
|
28
|
--
|
29
|
-- ---------------------------------------------------------------------
|
30
|
|
31
|
ENTITY c08s04b00x00p07n02i01310ent IS
|
32
|
END c08s04b00x00p07n02i01310ent;
|
33
|
|
34
|
ARCHITECTURE c08s04b00x00p07n02i01310arch OF c08s04b00x00p07n02i01310ent IS
|
35
|
type sigrec is
|
36
|
record
|
37
|
A1 : bit;
|
38
|
A2 : integer;
|
39
|
A3 : character;
|
40
|
A4 : boolean;
|
41
|
end record;
|
42
|
signal S1 : bit;
|
43
|
signal S2 : integer;
|
44
|
signal S3 : character;
|
45
|
signal S4 : boolean;
|
46
|
BEGIN
|
47
|
TESTING: PROCESS
|
48
|
BEGIN
|
49
|
(S1, S2, S3, S4) <= sigrec'('1', 1, '1', true);
|
50
|
wait for 1 ns;
|
51
|
assert NOT( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
|
52
|
report "***PASSED TEST: c08s04b00x00p07n02i01310"
|
53
|
severity NOTE;
|
54
|
assert ( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
|
55
|
report "***FAILED TEST: c08s04b00x00p07n02i01310 - A waveform element on the rigth-hand side must be the same as the base type of the aggregate."
|
56
|
severity ERROR;
|
57
|
wait;
|
58
|
END PROCESS TESTING;
|
59
|
|
60
|
END c08s04b00x00p07n02i01310arch;
|