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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_02.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               package project_util is
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                 -- code from book (in text)
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                 function "<" ( bv1, bv2 : bit_vector ) return boolean;
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                 subtype word is std_logic_vector(31 downto 0);
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                 -- end code from book
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               end package project_util;
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               package body project_util is
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                 function "<" ( bv1, bv2 : bit_vector ) return boolean is
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                   variable tmp1 : bit_vector(bv1'range) := bv1;
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                   variable tmp2 : bit_vector(bv2'range) := bv2;
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                 begin
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                   assert bv1'length = bv2'length
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                     report "vectors are of different length in ""<"" comparison"
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                     severity failure;
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                   tmp1(tmp1'left) := not tmp1(tmp1'left);
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                   tmp2(tmp2'left) := not tmp2(tmp2'left);
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                   return std.standard."<" ( tmp1, tmp2 );
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                 end function "<";
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               end package body project_util;
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-- code from book
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               library ieee;  use ieee.std_logic_1164.all;
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               use work.project_util.all;
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               entity limit_checker is
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                 port ( input, lower_bound, upper_bound : in word;
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                        out_of_bounds : out std_logic );
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               end entity limit_checker;
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--------------------------------------------------
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               architecture behavioral of limit_checker is
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                 subtype bv_word is bit_vector(31 downto 0);
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                 function word_to_bitvector ( w : in word ) return bv_word is
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                 begin
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                   return To_bitvector ( w, xmap => '0' );
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                 end function word_to_bitvector;
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               begin
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                 algorithm : process (input, lower_bound, upper_bound) is
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                 begin
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                   if "<" ( bv1 => word_to_bitvector(input),
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                            bv2 => word_to_bitvector(lower_bound) )
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                     or "<" ( bv1 => word_to_bitvector(upper_bound),
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                              bv2 => word_to_bitvector(input) ) then
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                     out_of_bounds <= '1';
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                   else
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                     out_of_bounds <= '0';
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                   end if;
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                 end process algorithm;
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               end architecture behavioral;
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-- end code from book
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               library ieee;  use ieee.std_logic_1164.all;
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               use work.project_util.all;
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               entity fg_21_02 is
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               end entity fg_21_02;
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               architecture test of fg_21_02 is
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                 signal input : word;
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                 signal out_of_bounds : std_logic;
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               begin
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                 dut : entity work.limit_checker(behavioral)
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                   port map ( input => input,
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                              lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
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                              out_of_bounds => out_of_bounds );
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                 stimulus : input <= X"00000000",
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                                     X"00000008" after 10 ns,
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                                     X"00000010" after 20 ns,
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                                     X"00000018" after 30 ns,
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                                     X"FFFFFFF8" after 40 ns,
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                                     X"FFFFFFF0" after 50 ns,
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                                     X"FFFFFF00" after 60 ns;
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               end architecture test;
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