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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package cell_attributes is
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type length is range 0 to integer'high
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units nm;
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um = 1000 nm;
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mm = 1000 um;
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mil = 25400 nm;
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end units length;
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type coordinate is record
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x, y : length;
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end record coordinate;
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attribute cell_position : coordinate;
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end package cell_attributes;
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entity CPU is
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end entity CPU;
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-- code from book
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architecture cell_based of CPU is
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component fpu is
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port ( -- . . . );
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-- not in book
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port_name : bit := '0' );
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-- end not in book
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end component;
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use work.cell_attributes.all;
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attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
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-- . . .
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begin
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the_fpu : component fpu
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port map ( -- . . . );
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-- not in book
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port_name => open );
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-- end not in book
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-- . . .
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end architecture cell_based;
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-- end code from book
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