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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_20_07 is
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end entity ch_20_07;
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----------------------------------------------------------------
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architecture test of ch_20_07 is
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  component multiplier is
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  end component multiplier;
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  type length is range 0 to integer'high
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    units nm;
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          um = 1000 nm;
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          mm = 1000 um;
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          mil = 25400 nm;
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    end units length;
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  type coordinate is record
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                       x, y : length;
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                     end record coordinate;
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  type orientation_type is (up, down, left, right);
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  attribute cell_allocation : string;
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  attribute cell_position : coordinate;
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  attribute cell_orientation : orientation_type;
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  -- code from book:
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  attribute cell_allocation of mult : label is "wallace_tree_multiplier";
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  attribute cell_position of mult : label is ( 1200 um, 4500 um );
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  attribute cell_orientation of mult : label is down;
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  -- end of code from book
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begin
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  mult : component multiplier;
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end architecture test;
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