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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_20_06 is
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end entity ch_20_06;
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----------------------------------------------------------------
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use std.textio.all;
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architecture test of ch_20_06 is
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37
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subtype encoding_type is bit_vector(1 downto 0);
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attribute encoding : encoding_type;
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begin
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process1 : process is
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-- code from book:
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type controller_state is (idle, active, fail_safe);
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type load_level is (idle, busy, overloaded);
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attribute encoding of idle [ return controller_state ] : literal is b"00";
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attribute encoding of active [ return controller_state ] : literal is b"01";
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attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
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-- end of code from book
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variable L : line;
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begin
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write(L, string'("process1"));
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writeline(output, L);
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write(L, idle [ return controller_state ] ' encoding);
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writeline(output, L);
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write(L, active [ return controller_state ] ' encoding);
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writeline(output, L);
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write(L, fail_safe [ return controller_state ] ' encoding);
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writeline(output, L);
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wait;
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end process process1;
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process2 : process is
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type controller_state is (idle, active, fail_safe);
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type load_level is (idle, busy, overloaded);
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attribute encoding of idle : literal is b"11";
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variable L : line;
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begin
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write(L, string'("process2"));
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writeline(output, L);
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write(L, idle [ return controller_state ] ' encoding);
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writeline(output, L);
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write(L, idle [ return load_level ] ' encoding);
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writeline(output, L);
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wait;
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end process process2;
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90
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end architecture test;
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