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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_20_05 is
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end entity ch_20_05;
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----------------------------------------------------------------
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architecture test of ch_20_05 is
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type stimulus_list is array (natural range <>) of integer;
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-- code from book:
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function "&" ( a, b : stimulus_list ) return stimulus_list;
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attribute debug : string;
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attribute debug of
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"&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
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"source_statement_step";
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type mvl is ('X', '0', '1', 'Z');
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type mvl_vector is array ( integer range <>) of mvl;
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function resolve_mvl ( drivers : mvl_vector ) return mvl;
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subtype resolved_mvl is resolve_mvl mvl;
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type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
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attribute builtin : builtin_types;
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attribute builtin of resolved_mvl : subtype is builtin_mvl;
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-- end of code from book
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function "&" ( a, b : stimulus_list ) return stimulus_list is
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begin
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return stimulus_list'(1 to 0 => 0);
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end function "&";
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function resolve_mvl ( drivers : mvl_vector ) return mvl is
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begin
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return drivers(drivers'left);
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end function resolve_mvl;
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begin
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end architecture test;
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