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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_18_fg_18_03.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library bv_utilities;
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package CPU_types is
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  subtype word is bit_vector(0 to 31);
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  subtype byte is bit_vector(0 to 7);
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  alias convert_to_natural is
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    bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
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  constant halt_opcode : byte := "00000000";
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  type code_array is array (natural range <>) of word;
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  constant code : code_array := ( X"01000000", X"01000000", X"02000000",
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				  X"01000000", X"01000000", X"02000000",
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				  X"00000000" );
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end package CPU_types;
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use work.CPU_types.all;
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entity CPU is
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end entity CPU;
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-- code from book
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architecture instrumented of CPU is
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  type count_file is file of natural;
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  file instruction_counts : count_file open write_mode is "instructions";
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begin
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  interpreter : process is
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                          variable IR : word;
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                        alias opcode : byte is IR(0 to 7);
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                        variable opcode_number : natural;
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                        type counter_array is array (0 to 2**opcode'length - 1) of natural;
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                        variable counters : counter_array := (others => 0);
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                        -- . . .
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                        -- not in book
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                        variable code_index : natural := 0;
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                        -- end not in book
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  begin
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    -- . . .    -- initialize the instruction set interpreter
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    instruction_loop : loop
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      -- . . .    -- fetch the next instruction into IR
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      -- not in book
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      IR := code(code_index);
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      code_index := code_index + 1;
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      -- end not in book
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      -- decode the instruction
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      opcode_number := convert_to_natural(opcode);
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      counters(opcode_number) := counters(opcode_number) + 1;
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      -- . . .
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      -- execute the decoded instruction
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      case opcode is
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        -- . . .
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        when halt_opcode => exit instruction_loop;
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                            -- . . .
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                            -- not in book
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        when others => null;
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                       -- end not in book
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      end case;
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    end loop instruction_loop;
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    for index in counters'range loop
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      write(instruction_counts, counters(index));
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    end loop;
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    wait;  -- program finished, wait forever
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  end process interpreter;
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end architecture instrumented;
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-- code from book
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