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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_18_fg_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_18_02_a is
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end entity fg_18_02_a;
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architecture writer of fg_18_02_a is
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begin
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  process is
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            type packet_file is file of bit_vector;
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          file stimulus_file : packet_file open write_mode is "test packets";
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  begin
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    write(stimulus_file, X"6C");
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    write(stimulus_file, X"05");
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    write(stimulus_file, X"3");
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    wait;
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  end process;
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end architecture writer;
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entity fg_18_02 is
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end entity fg_18_02;
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architecture test of fg_18_02 is
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  signal stimulus_network, stimulus_clock : bit;
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begin
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  clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
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  -- code from book
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  stimulate_network : process is
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                                type packet_file is file of bit_vector;
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                              file stimulus_file : packet_file open read_mode is "test packets";
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                              -- variable packet : bit_vector(1 to 2048);
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                              -- not in book (for testing only)
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                              variable packet : bit_vector(1 to 8);
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                              -- end not in book
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                              variable packet_length : natural;
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  begin
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    while not endfile(stimulus_file) loop
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      read(stimulus_file, packet, packet_length);
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      if packet_length > packet'length then
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        report "stimulus packet too long - ignored" severity warning;
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      else
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        for bit_index in 1 to packet_length loop
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          wait until stimulus_clock = '1';
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          stimulus_network <= not stimulus_network;
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          wait until stimulus_clock = '0';
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          stimulus_network <= stimulus_network xor packet(bit_index);
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        end loop;
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      end if;
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    end loop;
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    wait;  -- end of stimulation: wait forever
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  end process stimulate_network;
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  -- code from book
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end architecture test;
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