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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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               entity fg_18_01_a is
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               end entity fg_18_01_a;
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               architecture writer of fg_18_01_a is
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               begin
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                 process is
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                           subtype word is std_logic_vector(0 to 7);
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                         type load_file_type is file of word;
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                         file load_file : load_file_type open write_mode is "fg_18_01.dat";
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                 begin
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                   write(load_file, word'(X"00"));
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                   write(load_file, word'(X"01"));
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                   write(load_file, word'(X"02"));
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                   write(load_file, word'(X"03"));
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                   write(load_file, word'(X"04"));
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                   write(load_file, word'(X"05"));
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                   write(load_file, word'(X"06"));
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                   write(load_file, word'(X"07"));
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                   write(load_file, word'(X"08"));
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                   write(load_file, word'(X"09"));
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                   write(load_file, word'(X"0A"));
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                   write(load_file, word'(X"0B"));
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                   write(load_file, word'(X"0C"));
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                   write(load_file, word'(X"0D"));
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                   write(load_file, word'(X"0E"));
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                   write(load_file, word'(X"0F"));
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                   wait;
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                 end process;
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               end architecture writer;
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-- end not in book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity ROM is
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                 generic ( load_file_name : string );
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                 port ( sel : in std_logic;
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                        address : in std_logic_vector;
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                        data : inout std_logic_vector );
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               end entity ROM;
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--------------------------------------------------
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               architecture behavioral of ROM is
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               begin
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                 behavior : process is
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                                      subtype word is std_logic_vector(0 to data'length - 1);
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                                    type storage_array is
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                                      array (natural range 0 to 2**address'length - 1) of word;
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                                    variable storage : storage_array;
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                                    variable index : natural;
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                                    -- . . .    -- other declarations
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                                    type load_file_type is file of word;
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                                    file load_file : load_file_type open read_mode is load_file_name;
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                 begin
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                   -- load ROM contents from load_file
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                   index := 0;
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                   while not endfile(load_file) loop
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                     read(load_file, storage(index));
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                     index := index + 1;
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                   end loop;
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                   -- respond to ROM accesses
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                   loop
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                     -- . . .
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                   end loop;
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                 end process behavior;
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               end architecture behavioral;
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-- not in book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity fg_18_01 is
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               end entity fg_18_01;
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               architecture test of fg_18_01 is
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                 signal sel : std_logic;
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                 signal address : std_logic_vector(3 downto 0);
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                 signal data : std_logic_vector(0 to 7);
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               begin
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                 dut : entity work.ROM(behavioral)
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                   generic map ( load_file_name => "fg_18_01.dat" )
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                   port map ( sel, address, data );
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               end architecture test;
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-- end not in book
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