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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture detailed_timing of counter is
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  signal reset_ipd,                   -- data input port delayed
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    clk_ipd : bit;               -- clock input port delayed
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  signal q_zd : bit_vector(q'range);  -- q output with zero delay
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begin
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  input_port_delay : block is
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  begin
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    reset_ipd <= reset after tipd_reset;
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    clk_ipd <= clk after tipd_clk;
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  end block input_port_delay;
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  functionality : block is
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                          function increment ( bv : bit_vector ) return bit_vector is
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    variable result : bit_vector(bv'range) := bv;
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    variable carry : bit := '1';
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  begin
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    for index in result'reverse_range loop
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      result(index) := bv(index) xor carry;
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      carry :=  bv(index) and carry;
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      exit when carry = '0';
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    end loop;
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    return result;
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  end function increment;
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  signal next_count : bit_vector(q'range);
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  begin
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    next_count <= increment(q_zd) when reset_ipd = '0' else
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                  (others => '0');
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    q_zd <= next_count when clk_ipd = '1' and clk_ipd'event;
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  end block functionality;
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  output_port_delay : block is
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  begin
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    q <= q_zd after topd_q;
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  end block output_port_delay;
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  timing_checks : block is
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  begin
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    -- check setup time: reset before clk
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    -- . . .
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    -- check hold time: reset after clk
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    -- . . .
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  end block timing_checks;
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end architecture detailed_timing;
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-- not in book
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entity fg_16_13 is
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end entity fg_16_13;
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architecture test of fg_16_13 is
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  signal reset, clk : bit := '0';
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  signal q : bit_vector(3 downto 0);
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begin
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  dut : entity work.counter(detailed_timing)
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    generic map ( tipd_reset => 2 ns,
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                  tipd_clk => 3 ns,
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                  topd_q => 4 ns,
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                  tsetup_reset => 3 ns,
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                  thold_reset => 1 ns )
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    port map ( reset => reset, clk => clk, q => q );
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  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
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  reset <= '1' after 62 ns, '0' after 106 ns;
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end architecture test;
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-- end not in book
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