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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity computer_system is
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end entity computer_system;
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-- code from book
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architecture abstract of computer_system is
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  -- not in book
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  subtype word is bit_vector(31 downto 0);
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  type word_vector is array (natural range <>) of word;
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  function resolve_word ( drivers : word_vector ) return word is
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  begin
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    if drivers'length > 0 then
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      return drivers(drivers'left);
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    else
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      return X"00000000";
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    end if;
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  end function resolve_word;
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  -- end not in book
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  -- . . .
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  signal address_bus : resolve_word word bus;
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  signal hold_req : bit;
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  -- . . .
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  -- not in book
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  signal clk : bit := '0';
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  -- end not in book
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begin
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  cpu : block is
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                signal guard : boolean := false;
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              signal cpu_internal_address : word;
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              -- . . .
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  begin
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    cpu_address_driver:
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      address_bus <= guarded cpu_internal_address;
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    -- . . .    -- other bus drivers
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    controller : process is
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                           -- . . .
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    begin
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      -- . . .
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      -- . . .    -- determine when to disable cpu bus drivers
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      guard <= false;
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      wait on clk until hold_req = '0' and clk = '1';
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      guard <= true;  -- re-enable cpu bus drivers
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      -- . . .
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      -- not in book
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      wait until clk = '1';
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      -- end not in book
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    end process controller;
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    -- . . .    -- cpu datapath processes
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    -- not in book
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    cpu_internal_address <= X"11111111";
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    -- end not in book
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  end block cpu;
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  -- . . .    -- blocks for DMA and other modules
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  -- not in book
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  clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
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  -- end not in book
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end architecture abstract;
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-- end code from book
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