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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity latch is
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generic ( width : positive );
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port ( enable : in bit;
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d : in bit_vector(0 to width - 1);
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q : out bit_vector(0 to width - 1) );
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end entity latch;
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--------------------------------------------------
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architecture behavioral of latch is
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begin
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transfer_control : block ( enable = '1' ) is
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begin
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q <= guarded d;
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end block transfer_control;
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end architecture behavioral;
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-- not in book
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entity fg_16_09 is
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end entity fg_16_09;
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architecture test of fg_16_09 is
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signal enable : bit := '0';
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signal d, q : bit_vector(0 to 7);
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begin
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dut : entity work.latch(behavioral)
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generic map ( width => 8 )
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port map ( enable => enable, d => d, q => q );
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stimulus : process is
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begin
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wait for 10 ns;
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d <= X"11"; wait for 10 ns;
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enable <= '1'; wait for 10 ns;
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d <= X"AA"; wait for 10 ns;
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enable <= '0'; wait for 10 ns;
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d <= X"00"; wait for 10 ns;
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wait;
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end process stimulus;
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end architecture test;
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-- end not in book
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