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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_rf-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library bv_utilities;
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architecture behavior of reg_file is
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begin
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  reg: process ( a1, a2, a3, d3, write_en ) is
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                                              use work.dlx_instr.reg_index,
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                                              bv_utilities.bv_arithmetic.bv_to_natural;
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                                            constant all_zeros : dlx_word := X"0000_0000";
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                                            type register_array is array (reg_index range 1 to 31) of dlx_word;
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                                            variable register_file : register_array;
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                                            variable reg_index1, reg_index2, reg_index3 : reg_index;
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  begin
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    -- do write first if enabled
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    --
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    if To_bit(write_en) = '1' then
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      reg_index3 := bv_to_natural(To_bitvector(a3));
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      if reg_index3 /= 0 then
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        register_file(reg_index3) := To_X01(d3);
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      end if;
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    end if;
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    --
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    -- read port 1
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    --
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    reg_index1 := bv_to_natural(To_bitvector(a1));
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    if reg_index1 /= 0 then
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      q1 <= register_file(reg_index1) after Tac;
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    else
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      q1 <= all_zeros after Tac;
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    end if;
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    --
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    -- read port 2
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    --
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    reg_index2 := bv_to_natural(To_bitvector(a2));
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    if reg_index2 /= 0 then
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      q2 <= register_file(reg_index2) after Tac;
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    else
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      q2 <= all_zeros after Tac;
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    end if;
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  end process reg;
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end architecture behavior;
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