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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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architecture verifier of dlx_test is
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  use work.dlx_types.all;
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  component clock_gen is
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                        port ( phi1, phi2 : out std_logic;
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                               reset : out std_logic );
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  end component clock_gen;
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  component memory is
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                     port ( phi1, phi2 : in std_logic;
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                            a : in dlx_address;
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                            d : inout dlx_word;
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                            width : in dlx_mem_width;
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                            write_enable : in std_logic;
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                            burst : in std_logic := '0';
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                            mem_enable : in std_logic;
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                            ready : out std_logic );
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  end component memory;
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  component dlx is
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                  port ( phi1, phi2 : in std_logic;
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                         reset : in std_logic;
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                         halt : out std_logic;
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                         a : out dlx_address;
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                         d : inout dlx_word;
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                         width : out dlx_mem_width;
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                         write_enable : out std_logic;
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                         ifetch : out std_logic;
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                         mem_enable : out std_logic;
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                         ready : in std_logic );
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  end component dlx;
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  signal phi1, phi2, reset : std_logic;
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  signal a_behav : dlx_address;
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  signal d_behav : dlx_word;
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  signal halt_behav : std_logic;
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  signal width_behav : dlx_mem_width;
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  signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
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  signal a_rtl : dlx_address;
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  signal d_rtl : dlx_word;
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  signal halt_rtl : std_logic;
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  signal width_rtl : dlx_mem_width;
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  signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
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  signal ready_mem : std_logic;
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begin
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  cg : component clock_gen
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    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
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  mem : component memory
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    port map ( phi1 => phi1, phi2 => phi2,
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               a => a_behav, d => d_behav,
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               width => width_behav, write_enable => write_enable_behav,
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               burst => open,
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               mem_enable => mem_enable_behav, ready => ready_mem );
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  proc_behav : component dlx
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    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
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               a => a_behav, d => d_behav,
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               width => width_behav, write_enable => write_enable_behav,
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               ifetch => ifetch_behav,
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               mem_enable => mem_enable_behav, ready => ready_mem );
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  proc_rtl : component dlx
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    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
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               a => a_rtl, d => d_rtl,
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               width => width_rtl, write_enable => write_enable_rtl,
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               ifetch => ifetch_rtl,
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               mem_enable => mem_enable_rtl, ready => ready_mem );
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  verification_section : block is
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  begin
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    fwd_data_from_mem_to_rtl : 
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      d_rtl <= d_behav when mem_enable_rtl = '1'
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               and write_enable_rtl = '0' else
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               disabled_dlx_word;
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    monitor : process
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      variable write_command_behav : boolean;
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      variable write_command_rtl : boolean;
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    begin
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      monitor_loop : loop
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        -- wait for a command, valid on leading edge of phi2
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        wait until rising_edge(phi2)
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          and mem_enable_behav = '1' and mem_enable_rtl = '1';
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        --
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        -- capture the command information
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        write_command_behav := write_enable_behav = '1';
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        write_command_rtl := write_enable_rtl = '1';
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        assert a_behav = a_rtl
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          report "addresses differ";
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        assert write_enable_behav = write_enable_rtl
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          report "write enable states differ";
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        assert ifetch_behav = ifetch_rtl
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          report "instruction fetch states differ";
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        assert width_behav = width_rtl
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          report "widths differ";
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        if write_command_behav and write_command_rtl then
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          assert d_behav = d_rtl
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            report "write data differs";
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        end if;
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        --
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        -- wait for the response from memory
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        ready_loop : loop 
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          wait until falling_edge(phi2);
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          exit monitor_loop when reset = '1';
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          exit ready_loop when ready_mem = '1';
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        end loop ready_loop;
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      end loop monitor_loop;
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      --
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      -- get here when reset is asserted
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      wait until reset = '0';
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      --
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      -- process monitor now starts again from beginning
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    end process monitor;
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  end block verification_section;
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end architecture verifier;
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