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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.dlx_types.all,
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  work.alu_types.all,
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  work.reg_file_types.all;
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entity controller is
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  generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
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            debug : dlx_debug_control := none );
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  port ( phi1, phi2 : in std_logic;
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         reset : in std_logic;
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         halt : out std_logic;
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         width : out dlx_mem_width;
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         write_enable : out std_logic;
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         mem_enable : out std_logic;
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         ifetch : out std_logic;
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         ready : in std_logic;
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         alu_in_latch_en : out std_logic;
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         alu_function : out alu_func;
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         alu_zero, alu_negative, alu_overflow : in std_logic;
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         reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
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         reg_write : out std_logic;
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         c_latch_en : out std_logic;
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         a_latch_en, a_out_en : out std_logic;
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         b_latch_en, b_out_en : out std_logic;
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         temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
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         iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
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         pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
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         mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
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         mem_addr_mux_sel : out std_logic;
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         mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
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         mdr_mux_sel : out std_logic;
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         ir_latch_en : out std_logic;
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         ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
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         ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
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         ir_immed1_en, ir_immed2_en : out std_logic;
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         current_instruction : in dlx_word;
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         mem_addr : std_logic_vector(1 downto 0);
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         const1, const2 : out dlx_word );
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end entity controller;
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