Project

General

Profile

Download (1.32 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_15_alu.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
23
-- $Revision: 1.3 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
library ieee;
28
use ieee.std_logic_1164.all;
29

    
30
use work.dlx_types.all,
31
  work.alu_types.all;
32

    
33
entity alu is
34
  generic ( Tpd : delay_length );
35
  port ( s1 : in dlx_word;
36
         s2 : in dlx_word;
37
         result : out dlx_word;
38
         func : in alu_func;
39
         zero, negative, overflow : out std_logic );
40
end entity alu;
(256-256/510)