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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee; use ieee.std_logic_1164.all;
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entity DRAM_4M_by_4 is
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port ( a : in std_logic_vector(0 to 10);
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d : inout std_logic_vector(0 to 3);
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cs, we, ras, cas : in std_logic );
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end entity DRAM_4M_by_4;
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architecture chip_function of DRAM_4M_by_4 is
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begin
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d <= (others => 'Z');
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end architecture chip_function;
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-- code from book
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library chip_lib; use chip_lib.all;
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configuration down_to_chips of memory_board is
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for chip_level
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for bank_array
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for nibble_array
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for a_DRAM : DRAM
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use entity DRAM_4M_by_4(chip_function);
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end for;
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end for;
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end for;
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-- . . . -- configurations of other component instances
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end for;
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end configuration down_to_chips;
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-- end code from book
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