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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity D_flipflop is
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                 port ( clk : in std_logic;  d : in std_logic;
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                 q : out std_logic );
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               end entity D_flipflop;
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               architecture synthesized of D_flipflop is
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               begin
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                 q <= d when not clk'stable and (To_X01(clk) = '1') and 
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                      (To_X01(clk'last_value) = '0');
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               end architecture synthesized;
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               library ieee;  use ieee.std_logic_1164.all;
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               entity tristate_buffer is
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                 port ( a : in std_logic;
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                        en : in std_logic;
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                        y : out std_logic );
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               end entity tristate_buffer;
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               architecture synthesized of tristate_buffer is
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               begin
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                 y <= 'X' when is_X(en) else
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                      a  when To_X01(en) = '1' else
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                      'Z';
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               end architecture synthesized;
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-- code from book (in Figure 14-1)
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               library ieee;  use ieee.std_logic_1164.all;
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               entity register_tristate is
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                 generic ( width : positive );
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                 port ( clock : in std_logic;
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                        out_enable : in std_logic;
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                        data_in : in std_logic_vector(0 to width - 1);
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                        data_out : out std_logic_vector(0 to width - 1) );
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               end entity register_tristate;
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--------------------------------------------------
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               architecture cell_level of register_tristate is
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                 component D_flipflop is
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                                        port ( clk : in std_logic;  d : in std_logic;
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                                        q : out std_logic );
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                 end component D_flipflop;
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                 component tristate_buffer is
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                                             port ( a : in std_logic;
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                                                    en : in std_logic;
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                                                    y : out std_logic );
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                 end component tristate_buffer;
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               begin
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                 cell_array : for bit_index in 0 to width - 1 generate
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                   signal data_unbuffered : std_logic;
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                 begin
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                   cell_storage : component D_flipflop
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                     port map ( clk => clock, d => data_in(bit_index),
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                                q => data_unbuffered );
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                   cell_buffer : component tristate_buffer
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                     port map ( a => data_unbuffered, en => out_enable,
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                                y => data_out(bit_index) );
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                 end generate cell_array;
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               end architecture cell_level;
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-- end code from book (in Figure 14-1)
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-- code from book (in Figure 14-11)
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               library cell_lib;
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               configuration identical_cells of register_tristate is
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                 for cell_level
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                   for cell_array
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                   for cell_storage : D_flipflop
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                   use entity cell_lib.D_flipflop(synthesized);
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               end for;
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               for cell_buffer : tristate_buffer
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                 use entity cell_lib.tristate_buffer(synthesized);
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               end for;
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               end for;
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               end for;
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               end configuration identical_cells;
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-- code from book (in Figure 14-11)
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               library ieee;  use ieee.std_logic_1164.all;
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               entity fg_14_01 is
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               end entity fg_14_01;
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               architecture test of fg_14_01 is
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                 signal clk, en : std_logic;
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                 signal d_in, d_out : std_logic_vector(0 to 3);
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               begin
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                 dut : configuration work.identical_cells
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                   generic map ( width => d_in'length )
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                   port map ( clock => clk, out_enable => en,
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                              data_in => d_in, data_out => d_out );
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                 stimulus : process is
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                 begin
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                   wait for 10 ns;
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                   d_in <= "0000";  en <= '0';  clk <= '0';  wait for 10 ns;
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                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
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                   en <= '1', '0' after 5 ns;   wait for 10 ns;
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                   d_in <= "0101";              wait for 10 ns;
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                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
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                   en <= 'H', '0' after 5 ns;   wait for 10 ns;
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                   wait;
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                 end process stimulus;
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               end architecture test;
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-- end not in book
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