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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity nand3 is
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generic ( Tpd : delay_length );
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port ( a, b, c : in bit; y : out bit );
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end entity nand3;
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architecture basic of nand3 is
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begin
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y <= not (a and b and c) after Tpd;
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end architecture basic;
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library project_lib;
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library stimulus;
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use stimulus.stimulus_generators.all;
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entity misc_logic is
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end entity misc_logic;
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-- code from book
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architecture gate_level of misc_logic is
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component nand3 is
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generic ( Tpd : delay_length );
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port ( a, b, c : in bit; y : out bit );
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end component nand3;
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for all : nand3
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use entity project_lib.nand3(basic);
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-- . . .
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-- not in book
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signal sig1, sig2, sig3, out_sig : bit;
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signal test_vector : bit_vector(1 to 3);
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-- end not in book
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begin
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gate1 : component nand3
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generic map ( Tpd => 2 ns )
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port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
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-- . . .
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-- not in book
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all_possible_values(test_vector, 10 ns);
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(sig1, sig2, sig3) <= test_vector;
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-- end not in book
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end architecture gate_level;
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-- end code from book
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