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ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd
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ERROR: Parse error at line 87 column 18:
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77: -- code from book
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78: 
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79:                architecture detailed_timing of interlock_control is
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80: 
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81:                  component nor_gate is
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82:                                       generic ( input_width : positive );
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83:                                     port ( input : in std_logic_vector(0 to input_width - 1);
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84:                                            output : out std_logic );
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85:                  end component nor_gate;
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86: 
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87:                  for ex_interlock_gate : nor_gate
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                     ^
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88:                    use entity cell_lib.nor_gate(primitive)
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89:                    generic map ( width => input_width,
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90:                                  Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
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91: 
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92:                  -- . . .
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93: 
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94:                  -- not in book
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95:                  signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
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96:                  -- end not in book
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97: 
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WARN: Missing blame information for the following files:
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WARN:   * ch_13_fg_13_23.vhd
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WARN: This may lead to missing/broken features in SonarQube
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