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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_20.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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               entity control_section is
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               end entity control_section;
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-- end not in book
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               architecture structural of control_section is
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                 component reg is
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                                 generic ( width : positive );
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                               port ( clk : in std_logic;
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                                      d : in std_logic_vector(0 to width - 1);
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                                      q : out std_logic_vector(0 to width - 1) );
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                 end component reg;
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                 for flag_reg : reg
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                   use entity work.reg(gate_level)
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                   -- workaround for MTI bug mt023
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                   --  reverted for ghdl
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                   port map ( clock => clk, data_in => d, data_out => q );
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                   -- port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
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                 -- end workaround
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                 -- . . .
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                 -- not in book
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                 signal clock_phase1, zero_result, neg_result, overflow_result,
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                   zero_flag, neg_flag, overflow_flag : std_logic;
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                 -- end not in book
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               begin
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                 flag_reg : component reg
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                   generic map ( width => 3 )
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                   port map ( clk => clock_phase1,
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                              d(0) => zero_result, d(1) => neg_result,
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                              d(2) => overflow_result,
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                              q(0) => zero_flag, q(1) => neg_flag,
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                              q(2) => overflow_flag );
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                 -- . . .
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                 -- not in book
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                 stimulus : process is
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                 begin
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                   clock_phase1 <= '0';
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                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
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                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
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                   wait;
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                 end process stimulus;
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                 -- end not in book
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               end architecture structural;
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