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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity XYZ3000_cpu is
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  port ( clock : in bit;  addr_data : inout bit_vector(31 downto 0);
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  other_port : in bit := '0' );
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end entity XYZ3000_cpu;
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architecture full_function of XYZ3000_cpu is
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begin
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end architecture full_function;
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entity memory_array is
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  port ( addr : in bit_vector(25 downto 0);  other_port : in bit := '0' );
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end entity memory_array;
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architecture behavioral of memory_array is
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begin
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end architecture behavioral;
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-- code from book
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library chips;
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configuration intermediate of single_board_computer is
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  for structural
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    for cpu : processor
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      use entity chips.XYZ3000_cpu(full_function)
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        port map ( clock => clk, addr_data => a_d, -- . . . );
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                   -- not in book
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                   other_port => open );
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      -- end not in book
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    end for;
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    for main_memory : memory
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      use entity work.memory_array(behavioral);
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    end for;
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    for all : serial_interface
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      use open;
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    end for;
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    -- . . .
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  end for;
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end configuration intermediate;
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-- end code from book
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