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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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configuration counter_down_to_gate_level of counter is
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  for registered
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    for all : digit_register
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      use configuration work.reg4_gate_level;
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    end for;
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    -- . . .    -- bindings for other component instances
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  end for;  -- end of architecture registered
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end configuration counter_down_to_gate_level;
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-- not in book
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entity fg_13_07 is
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end entity fg_13_07;
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use work.counter_types.all;
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architecture test of fg_13_07 is
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  signal clk, clr : bit := '0';
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  signal q0, q1 : digit;
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begin
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  dut : configuration work.counter_down_to_gate_level
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    port map ( clk => clk, clr => clr,
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               q0 => q0, q1 => q1 );
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  clk_gen : clk <= not clk after 20 ns;
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  clr_gen : clr <= '1' after 95 ns,
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		   '0' after 135 ns;
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end architecture test;
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-- end not in book
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