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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity edge_triggered_Dff is
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  generic ( Tprop, Tsetup, Thold : delay_length );
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  port ( clk : in bit;  clr : in bit; d : in bit;
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  q : out bit );
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end entity edge_triggered_Dff;
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architecture basic of edge_triggered_Dff is
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begin
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  state_change : process (clk, clr) is
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  begin
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    if clr = '1' then
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      q <= '0' after Tprop;
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    elsif clk'event and clk = '1' then
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      q <= d after Tprop;
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    end if;
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  end process state_change;
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end architecture basic;
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architecture hi_fanout of edge_triggered_Dff is
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begin
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  state_change : process (clk, clr) is
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  begin
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    if clr = '1' then
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      q <= '0' after Tprop;
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    elsif clk'event and clk = '1' then
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      q <= d after Tprop;
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    end if;
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  end process state_change;
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end architecture hi_fanout;
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-- code from book
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entity reg4 is
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  port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
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  q : out bit_vector(0 to 3) );
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end entity reg4;
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--------------------------------------------------
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architecture struct of reg4 is
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  component flipflop is
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                       generic ( Tprop, Tsetup, Thold : delay_length );
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                     port ( clk : in bit;  clr : in bit;  d : in bit;
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                     q : out bit );
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  end component flipflop;
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begin
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  bit0 : component flipflop
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    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
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    port map ( clk => clk, clr => clr, d => d(0), q => q(0) );
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  bit1 : component flipflop
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    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
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    port map ( clk => clk, clr => clr, d => d(1), q => q(1) );
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  bit2 : component flipflop
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    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
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    port map ( clk => clk, clr => clr, d => d(2), q => q(2) );
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  bit3 : component flipflop
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    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
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    port map ( clk => clk, clr => clr, d => d(3), q => q(3) );
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end architecture struct;
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-- end code from book
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configuration fg_13_01 of reg4 is
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  for struct
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    -- code from book (in text)
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    for bit0, bit1 : flipflop
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      use entity work.edge_triggered_Dff(basic);
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    end for;
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    -- end code from book
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  end for;
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end configuration fg_13_01;
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