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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package cpu_types is
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  constant word_size : positive := 16;
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  constant address_size : positive := 32;
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  subtype word is bit_vector(word_size - 1 downto 0);
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  subtype address is bit_vector(address_size - 1 downto 0);
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  type status_value is ( halted, idle, fetch, mem_read, mem_write,
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                         io_read, io_write, int_ack );
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end package cpu_types;
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package bit_vector_unsigned_arithmetic is
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  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
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end package bit_vector_unsigned_arithmetic;
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package body bit_vector_unsigned_arithmetic is
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  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
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    alias norm1 : bit_vector(1 to bv1'length) is bv1;
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    alias norm2 : bit_vector(1 to bv2'length) is bv2;
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    variable result : bit_vector(1 to bv1'length);
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    variable carry : bit := '0';
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  begin
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    if bv1'length /= bv2'length then
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      report "arguments of different length" severity failure;
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    else
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      for index in norm1'reverse_range loop
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        result(index) := norm1(index) xor norm2(index) xor carry;
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        carry := ( norm1(index) and norm2(index) )
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                 or ( carry and ( norm1(index) or norm2(index) ) );
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      end loop;
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    end if;
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    return result;
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  end function "+";
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end package  body bit_vector_unsigned_arithmetic;
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-- code from book
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package DMA_controller_types_and_utilities is
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  alias word is work.cpu_types.word;
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  alias address is work.cpu_types.address;
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  alias status_value is work.cpu_types.status_value;
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  alias "+" is work.bit_vector_unsigned_arithmetic."+"
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    [ bit_vector, bit_vector return bit_vector ];
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  -- . . .
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end package DMA_controller_types_and_utilities;
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-- end code from book
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