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 Copyright (C) 1996 Morgan Kaufmann Publishers, Inc

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 This file is part of VESTs (Vhdl tESTs).

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 VESTs is free software; you can redistribute it and/or modify it

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 under the terms of the GNU General Public License as published by the

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 Free Software Foundation; either version 2 of the License, or (at

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 your option) any later version.

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 VESTs is distributed in the hope that it will be useful, but WITHOUT

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 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

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 for more details.

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 You should have received a copy of the GNU General Public License

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 along with VESTs; if not, write to the Free Software Foundation,

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 Inc., 59 Temple Place, Suite 330, Boston, MA 021111307 USA

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20

 

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 $Id: ch_09_ch_09_04.vhd,v 1.2 20011024 23:31:00 paw Exp $

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 $Revision: 1.2 $

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package arithmetic_ops is

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 code from book

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procedure increment ( bv : inout bit_vector; by : in integer := 1 );

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procedure increment ( int : inout integer; by : in integer := 1 );

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 end code from book

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end package arithmetic_ops;

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package body arithmetic_ops is

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procedure increment ( bv : inout bit_vector; by : in integer := 1 ) is

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begin

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end procedure increment;

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procedure increment ( int : inout integer; by : in integer := 1 ) is

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begin

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end procedure increment;

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end package body arithmetic_ops;

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entity ch_09_04 is

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end entity ch_09_04;

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library stimulus;

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use stimulus.stimulus_generators.all;

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architecture test of ch_09_04 is

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 code from book

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 MTI bug mt017

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 alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];

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alias int_increment is work.arithmetic_ops.increment [ integer, integer ];

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 workaround to avoid MTI bug mt018

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 alias "*" is "and" [ bit, bit return bit ];

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alias "*" is std.standard."and" [ bit, bit return bit ];

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 alias "+" is "or" [ bit, bit return bit ];

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alias "+" is std.standard."or" [ bit, bit return bit ];

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 alias "" is "not" [ bit return bit ];

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alias "" is std.standard."not" [ bit return bit ];

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 end workaround

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alias high is std.standard.'1' [ return bit ];

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 end code from book

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signal a, b, c, s : bit := '0';

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signal test_vector : bit_vector(1 to 3);

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signal test_high : bit := high;

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begin

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 code from book

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 workaround to avoid MTI bug mt018

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 s <= a * b + (a) * c;

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s <= (a and b) or ((not a) and c);

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 end workaround

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 end code from book

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stimulus : all_possible_values ( bv => test_vector,

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delay_between_values => 10 ns );

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(a, b, c) <= test_vector;

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end architecture test;
