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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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library ieee;
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use ieee.std_logic_1164.all;
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entity reg_ctrl is
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port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
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reg_rd, reg_wr : out std_ulogic );
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end entity reg_ctrl;
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architecture bool_eqn of reg_ctrl is
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begin
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rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
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rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
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and not cpu_clk;
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end architecture bool_eqn;
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-- end code from book
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entity fg_07_20 is
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end entity fg_07_20;
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library ieee;
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use ieee.std_logic_1164.all;
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library stimulus;
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architecture test of fg_07_20 is
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signal reg_addr_decoded, rd, wr, io_en,
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cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
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signal test_vector : std_ulogic_vector(1 to 5);
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use stimulus.stimulus_generators.all;
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begin
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dut : entity work.reg_ctrl
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port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
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stimulus_proc : process is
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begin
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all_possible_values( bv => test_vector,
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delay_between_values => 10 ns );
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wait;
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end process stimulus_proc;
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(reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
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end architecture test;
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